Voltage conversion circuit

ABSTRACT

A voltage conversion circuit incorporate many of what were previously discrete components into a single IC, whereby the number of externally disposed discrete components is reduced as much as possible to reduce the overall size while maintaining high power conversion efficiency. This is achieved by using multiple wells within wells, and coupling the wells to specific voltage potentials to protect the circuit from failure.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a voltage conversion circuitused, for example, in the power supply of a liquid crystal panel andconfigured to output two voltages, that is, a positive and negativevoltage, based on an input dc voltage.

[0003] 2. Description of the Related Art

[0004] A first example of a voltage conversion circuit of this typeaccording to the prior art (referred to below as first prior artcircuit) is shown in FIG. 29.

[0005] As shown in FIG. 29 this first prior art circuit has a timingsignal generator 1, MOS transistors Q1 to Q6 that are controllablyswitched ON/OFF by the output from the timing signal generator 1,capacitors C1 and C2 producing a positive voltage twice the dc inputvoltage Vin according to the ON/OFF operation of MOS transistors Q1 toQ4, capacitors C3 and C4 producing a negative voltage −1 times the dcinput voltage Vin according to the ON/OFF operation of MOS transistorsQ1, Q2, Q5, and Q6, and a level shift circuit 2.

[0006] MOS transistors Q1 and Q5 of MOS transistors Q1 to Q6 are n-type,and MOS transistors Q2 to Q4 and Q6 are p-type. As shown in the figure,level shift circuit 2 consists of resistors, diodes, and the like.

[0007] Note also that the timing signal generator 1 and MOS transistorsQ1 to Q4 enclosed in the dotted square in FIG. 29 in this first priorart circuit, , are integrated onto the same semiconductor substrate,forming an IC chip. The level shift circuit 2, MOS transistors Q5 andQ6, and capacitors C1 to C4 are separate components externally connectedto the IC chip.

[0008] The operation of this first prior art circuit is described nextwith reference to FIG. 29 to FIG. 31.

[0009] The timing signal generator 1 generates and supplies timingsignals (control signals) A, XB, XA2, XB2 to the gate of MOS transistorsQ1 to Q4, respectively, to switch the MOS transistors Q1 to Q4 ON orOFF. Timing signals A and XB from timing signal generator 1 are levelshifted by the level shift circuit 2, which outputs the resultingsignals AS and XBS to the gates of MOS transistors Q5 and Q6 to switchMOS transistors Q5 and Q6 ON or OFF.

[0010] This operation causes MOS transistors Q1, Q3, Q5 to be ON and MOStransistors Q2, Q4, Q6 to be off in period T1 shown in FIG. 30. Thecircuit equivalent to operation period T1 is shown in FIG. 31A.Capacitor C1 is charged by the dc source Vin. The positive outputvoltage VOUT1 is the sum of the source voltage Vin and the stored chargevoltage of capacitor C2. At the same time the charge of capacitor C3 isshared with capacitor C4, and the end voltage of capacitor C3 becomesthe negative output voltage VOUT2.

[0011] In period T2 in FIG. 30 MOS transistors Q2, Q4, Q6 switch on, andMOS transistors Q1, Q3, Q5 switch off. The circuit equivalent to periodT2 is shown in FIG. 31B. Capacitor C3 is charged by the dc source Vin,and the negative output voltage VOUT2 is the voltage across capacitorC4. At the same time, the charge of capacitor C1 is shared withcapacitor C2, and the positive output voltage VOUT1 becomes the sum ofthe source voltage Vin and the stored charge voltage of capacitor C1.The voltage drops VF are due to the forward voltage drops of the diodeswithin the level shift circuit 2. This first prior art circuit thusoperates as a charge-pump type dc-dc converter by simply repeating theoperation of periods T1 and T2.

[0012] As a result of this operation, the values of positive outputvoltage VOUTI and negative output voltage VOUT2 from this first priorart circuit can be determined from equations (1) and (2) where theground GND potential is 0 V.

VOUT1=Vin·2  (1)

VOUT2 =Vin·(−1)  (2)

[0013] where Vin is the dc input voltage.

[0014]FIG. 32 shows the configuration of the MOS transistors Q1 to Q4inside the dotted line in FIG. 29 integrated to a semiconductorsubstrate in this first prior art circuit.

[0015] As shown in FIG. 32, reference numeral 11 is a p-typesemiconductor substrate. An NMOS transistor Q1 with a source S, gate G,and drain D is formed in this p-type semiconductor substrate 12. Threen-wells 11 to 14 are also formed in p-type semiconductor substrate 11,and PMOS transistors Q2 to Q4 each having a source S, gate G, and drainD are formed in each of these n-wells 12 to 14.

[0016] Connections between parts of MOS transistors Q1 to Q4 and thep-type semiconductor substrate 11 are indicated by the bold lines inFIG. 32.

[0017] A second example of a voltage conversion circuit of this typeaccording to the prior art (referred to below as second prior artcircuit) is described next with reference to FIG. 33.

[0018] As shown in FIG. 33, this second prior art circuit replaces MOStransistors Q5 and Q6 of the first prior art circuit with diodes D1, D2,and eliminates the level shift circuit 2. The configuration of otherparts is identical to the configuration of the first prior art circuit,and further description thereof is thus omitted.

[0019] Operation of this second prior art circuit is basically the sameas that of the first prior art circuit except that since the switchingdevices are diodes, and not complementary MOS transistors, a voltagedrop, VFa, equivalent to the forward voltage drop of the diodes isintroduced at the output. Therefore, VOUT2 of this embodiment differsfrom that of the embodiment of FIG. 29 in that the negative outputvoltage VOUT2 is as shown in equation (3).

VOUT2=[Vin·(−1)]+[VFa·2]  (3)

[0020] where VFa is the forward voltage drop of diodes D1, D2.

[0021] A problem with the first prior art circuit as shown in FIG. 29 isthat it is not possible to reduce the overall size of the circuitbecause of the many externally connected components, including parts ofthe level shift circuit 2 and MOS transistors Q5 and Q6.

[0022] Furthermore, because a level shift circuit 2 is needed, the levelof timing signal A from timing signal generator 1 is gradually loweredby level shift circuit 2, resulting in signal AS (see FIG. 30) beingapplied to the gate of MOS transistor Q5. This drop increases if thefrequency of signal AS is low, and potentially adversely affects theoperation of MOS transistor Q5.

[0023] The second prior art circuit has an advantage over the firstprior art circuit in that there are fewer external parts. However, thenegative output voltage VOUT2 is decreased by the forward voltage VFacomponent of the diode as shown by equation (3), and power conversionefficiency thus drops.

OBJECTS OF THE INVENTION

[0024] Therefore, with consideration for the above problems, an objectof the present invention is to provide a voltage conversion circuit thatreduces the number of external parts as much as possible and thusenables an overall reduction in size while maintaining high powerconversion efficiency.

SUMMARY OF THE INVENTION

[0025] To resolve the above problems, a voltage conversion circuitincludes a plurality of MOS transistors that are switched ON/OFF tocharge a capacitance with an input dc voltage, and this charging voltageis used to convert the input dc voltage to a specific positive andnegative output voltage, wherein: the plural MOS transistors includePMOS and NMOS transistors for positive voltage conversion, and a NMOStransistor for negative voltage conversion; the NMOS transistors forpositive voltage conversion are formed in a p-type semiconductorsubstrate; the PMOS transistors for positive voltage conversion areformed in an n-type first well formed in the p-type semiconductorsubstrate; and the NMOS transistor for negative voltage conversion isformed in a p-type third well, which is formed in an n-type second wellformed in the p-type semiconductor substrate.

[0026] The present invention can thus form the MOS transistors used forvoltage conversion in the same p-type semiconductor substrate, and cantherefore reduce the external components to capacitors only. It istherefore possible to reduce the overall size while maintaining a highpower conversion efficiency.

[0027] The present invention can alternatively be implemented as avoltage conversion circuit having a plurality of MOS transistors thatare switched ON/OFF to charge a capacitance with an input dc voltage,and using this charging voltage to convert the input dc voltage to aspecific positive and negative output voltage, wherein: the plural MOStransistors include PMOS and NMOS transistors for positive voltageconversion, and an NMOS transistor for negative voltage conversion; aspecific NMOS transistor for positive voltage conversion is formed in ap-type semiconductor substrate; the PMOS transistors for positivevoltage conversion are formed in an n-type first well formed in thep-type semiconductor substrate; and a NMOS transistors for positivevoltage conversion other than said specific NMOS transistor, and theNMOS transistor for negative voltage conversion, are formed in a p-typethird well, which is formed in an n-type second well formed in thep-type semiconductor substrate.

[0028] This embodiment of the invention can thus form the MOStransistors used for voltage conversion in the same p-type semiconductorsubstrate, and can therefore reduce the external components tocapacitors only. It is therefore possible to reduce the overall sizewhile maintaining high power conversion efficiency.

[0029] Furthermore, the NMOS transistor for positive voltage conversionis also isolated from a substrate bias effect with the inventiondescribed in claim 2, and problems such as an increased threshold valuetherefore do not occur.

[0030] In a third embodiment of the present invention includes a voltageconversion circuit having a plurality of MOS transistors that areswitched ON/OFF to charge a capacitance with the input dc voltage, andusing this charging voltage to convert the input dc voltage to aspecific positive and negative output voltage, wherein: the plural MOStransistors include PMOS and NMOS transistors for positive voltageconversion, and PMOS and NMOS transistors for negative voltageconversion; the NMOS transistors for negative voltage conversion areformed in a p-type semiconductor substrate; the PMOS transistors forpositive voltage conversion and PMOS transistors for negative voltageconversion are formed in an n-type first well formed in the p-typesemiconductor substrate; and the NMOS transistors for positive voltageconversion are formed in a p-type third well, which is formed in ann-type second well formed in the p-type semiconductor substrate.

[0031] This third embodiment of the invention can thus form the MOStransistors used for voltage conversion in the same p-type semiconductorsubstrate, and can therefore reduce the external components tocapacitors only. It is therefore possible to reduce the overall sizewhile maintaining high power conversion efficiency.

[0032] Additionally, with the third embodiment of the present invention,substrate biasing to a potential lower than the ground potential isprevented, and PMOS transistors can therefore be used as the MOStransistors producing a negative potential.

[0033] Alternatively, a fourth embodiment of the present invention is avoltage conversion circuit having a plurality of MOS transistors thatare switched ON/OFF to charge a capacitance with the input dc voltage,and using this charging voltage to convert the input dc voltage to aspecific positive and negative output voltage, wherein: the plural MOStransistors include PMOS and NMOS transistors for negative voltageconversion, and PMOS transistors for positive voltage conversion; thePMOS transistors for negative voltage conversion are formed in an n-typesemiconductor substrate; the NMOS transistors for negative voltageconversion are formed in a p-type first well in the n-type semiconductorsubstrate; and the PMOS transistors for positive voltage conversion areformed in an n-type third well, which is formed in a p-type second wellformed in the n-type semiconductor substrate.

[0034] The fourth embodiment of the present invention can thus form theMOS transistors in the same n-type semiconductor substrate, and cantherefore reduce the external components to capacitors only. It istherefore possible to reduce the overall size while maintaining highpower conversion efficiency.

[0035] Alternatively, the first through fourth embodiments can furtherinclude an ON/OFF control means for switching the plural MOS transistorsON/OFF, the ON/OFF control means can be formed in the p-type or n-typesemiconductor substrate.

[0036] In any of the embodiments, it is also preferably that at leastone of the MOS transistors has an offset area in the semiconductorsubstrate around the gate insulation layer, the offset area being a lowconcentration impurity layer disposed below a LOCOS layer in thesemiconductor substrate.

[0037] By providing a low concentration impurity layer as an offsetregion below a LOCOS (local oxidation of silicon) layer in theinvention, the offset region can be made deep relative to the channelarea when compared with a configuration in which a LOCOS layer is notformed. As a result, the field around the drain is effectivelysaturated, the withstand voltage of the drain is increased, and a highwithstand voltage can be achieved.

[0038] Alternatively, in any of the embodiments, a voltage producing apotential is applied between the semiconductor substrate and second wellto assure that they remain in reverse bias condition, or at the samepotential during operation. Additionally, and a voltage producing areverse bias during operation is applied between the second well andthird well.

[0039] Alternatively, the invention may be implemented with a boostercircuit for boosting an input dc voltage n-fold and plurality of MOStransistors, outputting the boosted voltage of the booster circuit as apositive voltage, switching the plural MOS transistors ON/OFF to chargea capacitance with at least the boosted voltage of the booster circuit,and using this charging voltage to produce a negative voltage, wherein:the plural MOS transistors include PMOS and NMOS transistors used forgenerating the negative voltage; specific NMOS transistors are formed ina p-type semiconductor substrate; the PMOS transistors are formed in ann-type first well formed in the p-type semiconductor substrate; andspecific NMOS transistors are formed in a p-type third well, which isformed in an n-type second well formed in the p-type semiconductorsubstrate.

[0040] The invention in this embodiment can thus form the MOStransistors used for voltage conversion in the same p-type semiconductorsubstrate, and can therefore reduce the external components tocapacitors only. It is therefore possible to reduce the overall sizewhile maintaining high power conversion efficiency.

[0041] This same embodiment can further include an ON/OFF control meansfor switching the plural MOS transistors ON/OFF. The ON/OFF controlmeans and the booster circuit can be formed on the p-type semiconductorsubstrate.

[0042] Additionally, at least one of the MOS transistors can have anoffset area in the semiconductor substrate around the gate insulationlayer, the offset area being a low concentration impurity layer disposedbelow a LOCOS layer in the semiconductor substrate. This permits theinvention to achieve a high withstand voltage.

[0043] In this same embodiment, it is preferably that the semiconductorsubstrate and second well received a voltage to assure that they aremaintained reversed biased, or at the same potential, during operation.Also, a voltage producing a reverse bias condition between the secondwell and third well during operation, is preferably applied.

[0044] Lastly, the an n-type fourth well may further be formed in thethird well, and a PMOS transistor used for a logic circuit or a PMOStransistor used for generating a negative voltage is formed inside thefourth well.

[0045] Means of Resolution

[0046] This circuit has the timing signal generator and MOS transistorsintegrated into the same p-type semiconductor substrate, thus forming anIC chip, with capacitors externally connected to the IC chip. At leastone NMOS transistor is formed in the p-type semiconductor substrate,while PMOS transistors are formed in a first well of n-type conductivityformed in the p-type semiconductor substrate. Other NMOS transistors areformed in a third well of p-type conductivity, which is formed in asecond well of n-type conductivity formed in the p-type semiconductorsubstrate.

[0047] Other objects and attainments together with a fullerunderstanding of the invention will become apparent and appreciated byreferring to the following description and claims taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In the drawings wherein like reference symbols refer to likeparts.

[0049]FIG. 1 is a circuit diagram showing the circuit design of avoltage conversion circuit according to a first embodiment of thepresent invention;

[0050]FIG. 2 is a waveform diagram for the timing signal generator;

[0051]FIG. 3 is a section view showing the physical configuration of theMOS transistors;

[0052]FIG. 4 is a section view showing the configuration achieving ahigh withstand voltage in the MOS transistors in this first embodiment;

[0053]FIG. 5 is a section view showing another configuration achieving ahigh withstand voltage;

[0054]FIG. 6 is a section view showing yet another configurationachieving a high withstand voltage;

[0055]FIG. 7 is a circuit diagram showing the circuit design of avoltage conversion circuit according to a second embodiment of thepresent invention;

[0056]FIG. 8 is a waveform diagram for the timing signal generator;

[0057]FIG. 9 is a section view showing the physical configuration of theMOS transistors;

[0058]FIG. 10 is a circuit diagram showing the circuit design of avoltage conversion circuit according to a third embodiment of thepresent invention;

[0059]FIG. 11 is a waveform diagram for the timing signal generator;

[0060]FIGS. 12A and 12B show an operationally equivalent circuit;

[0061]FIG. 13 is a circuit diagram showing the circuit design of avoltage conversion circuit according to a fourth embodiment of thepresent invention;

[0062]FIG. 14 is a section view showing the physical configuration ofthe MOS transistors;

[0063]FIG. 15 is a circuit diagram showing the circuit design of avoltage conversion circuit according to a fifth embodiment of thepresent invention;

[0064]FIG. 16 is a section view showing the physical configuration ofthe MOS transistors;

[0065]FIG. 17 is a circuit diagram showing the circuit design of avoltage conversion circuit according to a sixth embodiment of thepresent invention;

[0066]FIG. 18 is a waveform diagram for the timing signal generator;

[0067]FIGS. 19A and 19B show an operationally equivalent circuit;

[0068]FIGS. 20A and 20B are a section view showing the physicalconfiguration of the MOS transistors;

[0069]FIG. 21 is a circuit diagram showing the circuit design of avoltage conversion circuit according to a seventh embodiment of thepresent invention;

[0070]FIG. 22 is a section view showing the physical configuration ofthe MOS transistors;

[0071]FIG. 23 is a circuit diagram showing the circuit design of a dc-dcconverter used in a voltage conversion circuit according to an eighthembodiment of the present invention;

[0072]FIG. 24 is a circuit diagram showing the circuit design of avoltage conversion circuit according to a ninth embodiment of thepresent invention;

[0073]FIG. 25 is a circuit diagram showing the circuit design of avoltage conversion circuit according to a tenth embodiment of thepresent invention;

[0074]FIG. 26 is a circuit diagram showing the internal configuration ofthe operational amplifier;

[0075]FIG. 27 is a circuit diagram showing another internalconfiguration for the operational amplifier;

[0076]FIG. 28 is a circuit diagram showing the circuit configuration ofa voltage conversion circuit according to an eleventh embodiment of thepresent invention;

[0077]FIG. 29 is a circuit diagram showing the configuration of a firstconventional circuit;

[0078]FIGS. 30A and 30B show the output waveform of the timing signalgenerator;

[0079]FIG. 31 shows an operationally equivalent circuit;

[0080]FIG. 32 is a section view showing the physical configuration ofthe MOS transistors; and

[0081]FIG. 33 is a circuit diagram showing the configuration of a secondconventional circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0082] A first embodiment of a voltage conversion circuit according tothe present invention is described below with reference to FIG. 1 toFIG. 3.

[0083] With reference to FIG. 1, a voltage conversion circuit accordingto the first embodiment of the present invention has a timing signalgenerator 25, MOS transistors Q11 to Q16ON/OFF, and capacitors C1 to C4configured to generate a positive output voltage VOUT1 and a negativeoutput voltage VOUT2 based on dc input voltage Vin. Transistors Q11 toQ16 are switched ON/OFF in accordance with their appropriate timingsignals XB2, XA2, XB, A, B3 and A3 from timing signal generator 15.

[0084] As further described below, the area enclosed in the dotted linein FIG. 1, that is, timing signal generator 25 and MOS transistors Q11to Q16, are integrated onto the same p-type semiconductor substrate, andare thus configured as IC chip 20. Capacitors C1 to C4 are discretecomponents externally connected to IC chip 20.

[0085] The timing signal generator 25 generates timing signals XB2, XA2,XB, A, B3, and A3 as shown in FIG. 2 to control the ON/OFF state oftheir corresponding MOS transistors Q11 to Q16.

[0086] MOS transistors Q11 to Q14 are used to convert dc input voltageVin to positive output voltage VOUT1, and MOS transistors Q11, Q12, Q15,and Q16 are used to convert dc input voltage Vin to negative outputvoltage VOUT2.

[0087] MOS transistors Q11 and Q12 are used for conversion to bothpositive and negative output voltages in this example, but it will benoted that another pair of MOS transistors could be provided so that MOStransistors Q11 and Q12 are used to convert the input voltage to onlyone of a positive or negative output voltage.

[0088] Yet more specifically, NMOS transistor Q11 and PMOS transistorQ12 are connected between ground line 21 and input line 22 with theirrespective drain nodes coupled together, as shown in FIG. 1. PMOStransistor Q13 and PMOS transistor Q14 are connected between input line22 and output line 23, with the drain node of transistor Q14 coupled tothe source node of transistor Q13. NMOS transistor Q15 and NMOStransistor Q16 are connected between ground line 21 and output line 24,with the drain node of transistor Q15 coupled to the source node of Q16.The timing signals XB2, XA2, XB, A, B3, and A3 from timing signalgenerator 25 are applied to the gates of MOS transistors Q11 to Q16.Capacitor C1 is connected to the node between NMOS transistor Q11 andPMOS transistor Q12 and the node between PMOS transistor Q13 and PMOStransistor Q14. Capacitor C2 is connected between input line 22 andoutput line 23. Capacitor C3 is connected to the node between NMOStransistor Q11 and PMOS transistor Q12 and the node between NMOStransistor Q15 and NMOS transistor Q16. Capacitor C4 is connectedbetween ground line 21 and output line 24.

[0089] As noted above, MOS transistors Q11 to Q16 are integrated to thesame p-type semiconductor substrate in the voltage conversion circuitaccording to this first embodiment, and the configuration thereof isdescribed next below.

[0090] In FIG. 3 reference numeral 31 is the p-type semiconductorsubstrate. Two n-type wells 32 and 33 are formed in the p-typesemiconductor substrate 31, and two p-type wells 34 and 35 are formed inn-type well 33.

[0091] NMOS transistor Q11 having a source S, gate G, and drain D isformed in p-type semiconductor substrate 31. PMOS transistor Q12 havinga source S, gate G, and drain D is formed in n-type well 32. NMOStransistors Q15 and Q16 each having a source S, gate G, and drain D areformed respectively in p-type wells 34 and 35. MOS transistors Q13 andQ14 shown in FIG. 1 are configured identically to MOS transistor Q12shown in FIG. 3, and are therefore not shown in FIG. 3.

[0092] Wells 33, 34, 35 are designed with consideration for thewithstand voltage and threshold value of the MOS transistors formed inwells 33, 34, and the pass-through voltage and junction voltage betweenthe wells. The following description assumes that the MOS transistorwithstand voltage is at least 10 V, and is preferably 20 V to 30 V.

[0093] The depth of the wells 33, 34, and 35 is determined withconsideration for the MOS transistor withstand voltage and thepass-through voltage between the p-type semiconductor substrate 31 andwells 34/35. In this example the depth of well 33 is 15 μm to 18 μm andthe depth of wells 34/35 is 6 μm to 8 μm.

[0094] The impurity concentration of wells 33, 34, and 35 is determinedaccording to the threshold value and withstand voltage of the MOStransistors. The surface concentration of impurities in well 33 is, forexample, 1×10¹⁶ to 3×10¹⁶ atms/cm³, and the surface concentration ofimpurities in wells 34/35 is 1×10¹⁶ to 3×10¹⁶ atms/cm³.

[0095] Wells 34 and 35 are shallower than well 33, and are preferably ½to ⅓ the depth of well 33 considering the MOS transistor withstandvoltage and the passthrough voltage between p-type semiconductorsubstrate 31 and wells 34/35.

[0096] It should be noted that the configuration of these wells 33 to 35also applies to the wells equivalent to wells 33 to 35 formed in thesemiconductor substrate in each of the embodiments described below.

[0097] The parts of MOS transistors Q15 and Q16 in FIG. 3 areelectrically connected as shown in FIG. 1, and the parts of MOStransistors Q11 and Q12 are electrically connected as shown in FIG. 1.

[0098] Negative output voltage VOUT2 is applied to p-type well 34 and dcinput voltage Vin is applied to n-type well 33 so that the pn junctionof p-type well 34 and n-type well 33 is reversed biased during use asshown in FIG. 3.

[0099] In addition, ground potential GND is applied to p-type well 35and dc input voltage Vin is applied to n-type well 33 to that the pnjunction of p-type well 35 and n-type well 33 is reverse biased duringuse.

[0100] Furthermore, ground potential GND is applied to p-typesemiconductor substrate 31 and dc input voltage Vin is applied to n-typewell 33 so that the pn junction of p-type semiconductor substrate 31 andn-type well 33 is reverse biased when used.

[0101] Yet further, ground potential GND is applied to p-typesemiconductor substrate 31 and dc input voltage Vin is applied to n-typewell 32 so that the pn junction of p-type semiconductor substrate 31 andn-type well 32 is reverse biased during use.

[0102] Note that the relationship between dc input voltage Vin, groundpotential GND, and negative output voltage VOUT2, is Vin>GND>VOUT2.

[0103] Potential is applied to each well in the configuration shown inFIG. 3 so that there is a reverse bias between n-type wells, but it isalso possible to apply the ground potential GND to n-type well 33 sothat n-type well 33 and p-type semiconductor substrate 31 are set to thesame potential.

[0104] The operation of the first embodiment thus comprised is describednext with reference to the figures.

[0105] The timing signal generator 25 generates timing signals XB2, XA2,XB, A, B3, and A3 as shown in FIG. 2, supplies the timing signals to thegate of corresponding MOS transistors Q11 to Q16, and thereby controlsthe ON/OFF state of MOS transistors Q11 to Q16.

[0106] As a result of this control, MOS transistors Q11, Q13, Q15 are ONand MOS transistors Q12, Q14, Q16 are OFF in period T1 in FIG. 2, andthe equivalent circuit is as shown in FIG. 31A. As shown in FIG. 2, inperiod T2, MOS transistors Q12, Q14, Q16 are ON and MOS transistors Q11,Q13, Q15 are OFF, and the equivalent circuit is as shown in FIG. 31B.

[0107] By repeating the operation of periods T1 and T2, this firstembodiment operates as a charge pump type dc-dc converter.

[0108] As a result of this operation, positive output voltage VOUT1 andnegative output voltage VOUT2 in this first embodiment are as shown inequations (1) and (2) above if the ground potential GND is 0 V.

[0109] As described above, MOS transistors Q15 and Q16 used to producenegative output voltage VOUT2 in this first embodiment are n-type, andthese NMOS transistors Q15 and Q16 are formed by forming an n-type well33 inside a p-type semiconductor substrate 31, forming p-type wells 34and 35 inside the n-type well 33, and then forming the NMOS transistorsQ15 and Q16 inside the p-type wells 34 and 35. In addition, thejunctions between p-type wells 34 and 35 and the n-type well 33 arereverse biased, the junction between p-type semiconductor substrate 31and n-type well 33 is reverse biased, and the junctions are usedelectrically separated. Note that n-type well 33 and p-typesemiconductor substrate 31 can have the same potential.

[0110] It is therefore possible with this first embodiment to form thetiming signal generator 25 and MOS transistors Q11 to Q16 in a p-typesemiconductor substrate 31 in a single IC chip, and the conventionallyneeded level shift circuit and MOS transistors of the prior art can beomitted. The only required external components are capacitors C1 to C4.It is therefore possible to reduce the overall size while maintaininghigh power conversion efficiency.

[0111] Alternate configurations as shown in FIGS. 4 to 6 are preferableas a means of achieving a higher withstand voltage in MOS transistorsQ11 to Q16 in this first embodiment. This configuration is described asapplied to MOS transistor Q15, as a typical example of transistorsQ11-Q16.

[0112]FIG. 4 shows an example in which a high withstand voltage isachieved by using a LOCOS offset structure for MOS transistor Q15.

[0113] More specifically, in this embodiment, MOS transistor Q15 has agate insulation layer 37 formed at a specific location on p-type well 34with gate G formed on this gate insulation layer 37. An offset LOCOSlayer 38 is formed around gate insulation layer 37, and an offsetimpurity layer 39 is formed below this offset LOCOS layer 38 from a lowconcentration n-type impurity layer. The source S and drain D are formedfrom a high concentration n-type impurity layer around the outside ofthis offset LOCOS layer 38.

[0114] Also shown in FIG. 4 are element-isolating LOCOS layer 40 forisolating MOS transistor Q15 from other MOS transistors, and a lowconcentration n-type impurity layer 41 formed below thiselement-isolating LOCOS layer 40.

[0115] This gate insulation layer 37 preferably has a film thickness of60 nm to 80 nm when a voltage of at least 10 V, or more specifically avoltage of 10 V to 30 V, is applied, although the specific thicknesswill depend upon the required MOS transistor withstand voltage.

[0116]FIG. 5 shows a MOS transistor Q15 in which a high withstandvoltage is achieved by using a drain over structure. That is, the bottomside of source S and drain D in this MOS transistor Q15 is surrounded bya low concentration n-type impurity 42 and 42, respectively.

[0117]FIG. 6 shows a MOS transistor Q15 in which an even higherwithstand voltage is achieved by using both a LOCOS offset structure, asshown in FIG. 4, and a drain over structure, as shown in FIG. 5.

[0118] More specifically, the MOS transistor Q15 of FIG. 6 has offsetLOCOS layer 38 formed around the gate insulation layer 37, and offsetimpurity layer 39, which is a low concentration n-type impurity layer,formed below this offset LOCOS layer 38. A low concentration n-typeimpurity layer 43 is also formed below the element-isolating LOCOS layer40, source S, and offset impurity layer 39, and a low concentrationn-type impurity layer 43 is formed below the element-isolating LOCOSlayer 40, drain D, and offset impurity layer 39.

[0119] The structures shown in FIG. 4 to FIG. 6 can also be applied tothe MOS transistors in the embodiments described below, and a highwithstand voltage can be achieved by such applications.

[0120] A second embodiment of a voltage conversion circuit according tothe present invention is described next with reference to FIG. 7 to FIG.9.

[0121] The voltage conversion circuit according to this secondembodiment replaces PMOS transistor Q12 of the first embodiment shown inFIG. 1 with an NMOS transistor Q17 as shown in FIG. 7, and the timingsignal generator 25A produces the timing signals shown in FIG. 8 andapplies timing signal B2 to the gate of MOS transistor Q17 (see FIG. 8).

[0122] The NMOS transistors Q11 and 17 in the voltage conversion circuitaccording to the second embodiment are configured as shown in FIG. 9.

[0123] As shown in FIG. 9 reference numeral 31 identifies a p-typesemiconductor substrate, an n-type well 45 is formed in this p-typesemiconductor substrate 31, and a p-type well 46 is formed in thisn-type well 45. NMOS transistor Q17 having a source S, gate G, and drainD is then formed in p-type well 46. In addition, NMOS transistor Q11having source S, gate G, and drain D is formed in p-type semiconductorsubstrate 31.

[0124] The drain D voltage of MOS transistor Q11 and the source Svoltage of MOS transistor Q17 are applied to p-type well 46, and groundpotential GND is applied to n-type well 45 to reverse bias the pnjunction of p-type well 46 and n-type well 45.

[0125] The internal configuration of other parts of the IC chip 20A ofthis second embodiment is the same as in IC chip 20 according to thefirst embodiment, like parts are identified by like reference numerals,and further description is therefore omitted. The operation of thissecond embodiment is also the same as the operation of the firstembodiment, and description thereof is therefore also omitted.

[0126] It will thus be apparent that MOS transistors Q11 and Q17 aren-type in this second embodiment, NMOS transistor Q11 is formed in thep-type semiconductor substrate 31 as shown in FIG. 9, and NMOStransistor Q17 is formed inside p-type well 46, which is formed inn-type well 45, which is formed in the p-type semiconductor substrate 31as shown in FIG. 9. Moreover, the junction between p-type well 46 andn-type well 45 is used reverse biased so that the elements are usedelectrically separated.

[0127] As a result, there is no substrate bias effect on MOS transistorQ17, there is no concern about an increase in the threshold value, andthe overall size of this second embodiment can be reduced as compared tothe first embodiment.

[0128] A voltage conversion circuit according to a third embodiment ofthe present invention is described next with reference to FIG. 10 toFIG. 12.

[0129] The voltage conversion circuit according to this third embodimenthas a circuit design as shown in FIG. 10, and based on the dc inputvoltage Vin outputs a positive output voltage VOUT1 at a voltage levelthree times dc input voltage Vin and outputs a negative output voltageVOUT2 at a voltage level −2 times the dc input voltage Vin.

[0130] As shown in FIG. 10, the voltage conversion circuit of this thirdembodiment is therefore based on the structure of the first embodimentshown in FIG. 1, adding to this basic circuit MOS transistors Q21 to Q24and capacitors C5 and C6, and replacing timing signal generator 25 withtiming signal generator 25C.

[0131] The physical structure of MOS transistors Q11 to Q16 is thereforeidentical to the MOS transistors Q11 to Q16 of the first embodiment.

[0132] To describe the physical structure of MOS transistors Q21 to Q24,MOS transistor Q21 is identical in structure to MOS transistor Q14, andMOS transistor Q22 is identical in structure to MOS transistor Q15. Inaddition, MOS transistors Q23 and Q24 are identical in structure to MOStransistors Q11 and Q12.

[0133] The timing signal generator 25C generates timing signals XB2,XA2, XB, A, XA, B, B3, and A3, applies the timing signals to the gatesof MOS transistors Q11 to Q16 and Q21 to Q24 to ON/OFF controls the MOStransistors.

[0134] The configuration of other parts of the IC chip 20B of this thirdembodiment is basically the same as in IC chip 20 according to the firstembodiment, like parts are identified by like reference numerals, andfurther description is therefore omitted.

[0135] An example of the operation of this third embodiment is describednext with reference to FIG. 10 to FIG. 12.

[0136] The timing signal generator 25C generates timing signals XB2,XA2, XB, A, XA, B, B3, and A3 as shown in FIG. 11, applies the timingsignals to the gates of corresponding MOS transistors Q11 to Q16 and Q21to Q24, and thus switches the MOS transistors Q11 to Q16 and Q21 to Q24ON and OFF.

[0137] As a result of this control, MOS transistors Q11, Q13, Q21, Q15,Q24 are ON in period T1 shown in FIG. 11, and MOS transistors Q12, Q14,Q16, Q22, Q23 are OFF. The period T1 equivalent circuit is shown in FIG.12 (A).

[0138] As a result, capacitor C1 is charged by dc source voltage Vin inperiod T1 and the charge of capacitor C5 in the previous period T2 movesto capacitor C2. The positive output voltage VOUT1 at this time is thesum of dc input voltage Vin and both end voltages of capacitor C5.

[0139] Also in period T1 capacitor C6 is charged by the voltage sum ofthe dc source voltage Vin and the stored charge voltage of capacitor C3from the previous period T2. The negative output voltage VOUT2 at thistime is the voltage across capacitor C4.

[0140] In period T2 in FIG. 11 MOS transistors Q12, Q14, Q16, Q22, Q23are ON and MOS transistors Q11, Q13, Q21, Q15, Q24 are OFF. The periodT2 equivalent circuit is as shown in FIG. 12(B).

[0141] Capacitor C5 is therefore charged in period T2 by the voltage sumof the dc source voltage Vin and the stored charge voltage of capacitorC1 from period T1. The positive output voltage VOUT1 at this time istherefore the sum of dc input voltage Vin and the voltage acrosscapacitor C2.

[0142] Also in period T2, capacitor C3 is charged by dc input voltageVin, and the charge of capacitor C6 stored in period T1 is shared withcapacitor C4. The negative output voltage VOUT2 at this time is thevoltage of both ends of capacitor C6.

[0143] As a result of this operation, the positive output voltage VOUT1and negative output voltage VOUT2 in this third embodiment are as shownin equations (4) and (5).

VOUT1=(3)·Vin  (4)

VOUT2=(−2)·Vin  (5)

[0144] As described above, timing signal generator 25C and MOStransistors Q11 to Q16 and Q21 to Q24 can be integrated to a p-typesemiconductor substrate in this third embodiment, thus forming an ICchip, and the only required external parts are capacitors C1 to C6. As aresult, the overall size can be reduced.

[0145] A voltage conversion circuit according to a fourth embodiment ofthe present invention is described next with reference to FIG. 13 andFIG. 14.

[0146] The voltage conversion circuit according to this fourthembodiment replaces the NMOS transistors Q15 and Q16 of the thirdembodiment shown in FIG. 10 with PMOS transistors Q25 and Q26 as shownin FIG. 13, and replaces timing signal generator 25C with timing signalgenerator 25D.

[0147] Timing signal generator 25D produces the timing signals similarto the timing signals of generator 25C with the exception that thetiming signal B3 that is coupled to transistor Q16 in FIG. 10 isreplaced with new timing signal XB3 coupled to transistor Q26 in FIG.13, and timing signal A3 that is coupled to transistor Q15 in FIG. 10 isreplaced with new timing signal XA3 coupled to transistor Q25 in FIG.13. In other words, timing signals XA3 and XB3 are applied to the gatesof PMOS transistors Q25 and Q26 to control their ON/OFF operation. Notethat these timing signals XA3 and XB3 are the inverse of timing signalsA3 and B3 generated by timing signal generator 25C (see FIG. 11).

[0148] The physical structure of the embodiment of FIG. 13 is describednext with particular reference to MOS transistors Q25 and Q26, as shownin FIG. 14.

[0149] In FIG. 14 reference numeral 31 is a p-type semiconductorsubstrate. Also, n-type wells 61 to 63 are formed in this p-typesemiconductor substrate 31, and p-type well 64 is formed in n-type well63. An NMOS transistor Q22 with source S, gate G, and drain D is formedin p-type semiconductor substrate 31. PMOS transistors Q25, Q26, Q12each having a source S, gate G, and drain D are formed in correspondingn-type wells 61, 62, 63. NMOS transistor Q11 with source S, gate G, anddrain D is formed in p-type well 64.

[0150] This fourth embodiment applies the negative output potentialVOUT2 of output line 24 to p-type semiconductor substrate 31, appliesground potential GND of ground line 21 to n-type well 62 and p-type well64, and applies dc input voltage Vin of input line 22 to n-type well 63.The pn junctions between wells, and the pn junction between well andp-type semiconductor substrate are thus used with a reverse bias.

[0151] MOS transistors Q25 and Q26 in this fourth embodiment are p-typetransistors formed in n-type wells 61 and 62, as shown in FIG. 14.Furthermore, NMOS transistor Q11 is formed in p-type well 64, as shownin FIG. 14. In addition, the ground potential GND (0 V) of ground line21 is applied to p-type well 64 and n-type well 62.

[0152] It is therefore possible with this fourth embodiment to form aPMOS transistor without causing a reverse bias to a potential below theground line 21, and the overall size can be reduced as in the thirdembodiment.

[0153] A voltage conversion circuit according to a fifth embodiment ofthe present invention is described next with reference to FIG. 15 andFIG. 16.

[0154] The voltage conversion circuit according to this fifth embodimenthas a timing signal generator 25, MOS transistors Q31 to Q36 that havetheir ON/OFF state controlled by the timing signals from timing signalgenerator 25, and capacitors C1 to C4 as shown in FIG. 15. Timing signalgenerator 25 and MOS transistors Q31 to Q36 enclosed in the dotted linein FIG. 15 are integrated to the same n-type semiconductor substrate asfurther described below, and thus form IC chip 20D.

[0155] This fifth embodiment generates a lx positive output voltageVOUT1 and a −2× negative output voltage VOUT2 based on negative dc inputvoltage Vin.

[0156] The physical structure of MOS transistors Q31 to Q36 is describednext with reference to FIG. 16.

[0157] In FIG. 16 reference numeral 51 is an n-type semiconductorsubstrate 51. Two p-type wells 52 and 53 are formed in this n-typesemiconductor substrate 51 and two n-type wells 54 and 55 are formed inp-type well 53.

[0158] PMOS transistor Q31 with source S, gate G, and drain D is formedin n-type semiconductor substrate 51. NMOS transistor Q32 with source S,gate G, and drain D is formed in p-type well 52. PMOS transistors Q35and Q36 each having a source S, gate G, and drain D are formed in n-typewells 54 and 55, respectively. NMOS transistors Q33 and Q34 shown inFIG. 15 are constructed identically to MOS transistor Q32 shown in FIG.16, and are therefore omitted in FIG. 16.

[0159] As shown in FIG. 16, specific voltages are applied to reversebias the well-well pn junction and the well to n-type semiconductorsubstrate pn junction. Note that the potential of p-type well 53 can beset to GND so that p-type well 53 and n-type semiconductor substrate 51are the same potential.

[0160] With this fifth embodiment of the invention configured asdescribed above, the timing signal generator 25 and MOS transistors Q31to Q36 can be formed on the n-type semiconductor substrate 51 to createan IC chip, and the only necessary external parts are thereforecapacitors C1 to C4. As a result, the overall size can be reduced.

[0161] A sixth embodiment of a voltage conversion circuit according tothe present invention is described next with reference to FIG. 17 toFIG. 20.

[0162] As shown in FIG. 17, the voltage conversion circuit according tothis sixth embodiment has a charge pump-type n-fold booster circuit 71for boosting the dc input voltage VC N-times, timing signal generator25E, MOS transistors Q41 to Q48 whose ON/OFF state is determined by thetiming signals output from timing signal generator 25E, and capacitorsCP1, CB0, CB1, CP2, CB2. The structure is configured to output apositive output voltage V3 at output line 75, negative output voltagesVDDy at output line 76, and negative output voltage MV3 at output line77.

[0163] In the voltage conversion circuit according to this sixthembodiment, the parts enclosed in the dotted line in FIG. 17, that is,n-fold booster circuit 71, timing signal generator 25E, and MOStransistors Q41 to Q48 are integrated on the same p-type semiconductorsubstrate, thus forming IC chip 20E. Capacitors CP1, CB0, CB1, CP2, andCB2 are discrete components externally connected to IC chip 20E.

[0164] If the n-fold booster circuit 71 has a gain of three times, forexample, the n-fold booster circuit 71 comprises the parts of thevoltage conversion circuit shown in FIG. 10 for generating a positivevoltage.

[0165] The timing signal generator 25E generates timing signals XB2, A2,XB1, A1, B3, and A3, and applies these timing signals to switch the MOStransistors Q41 to Q48 ON and OFF.

[0166] MOS transistors Q41 to Q44 are used to generate negative outputvoltage MV3, and MOS transistors Q45 to Q48 are used to generatenegative output voltage VDDy.

[0167] More specifically, NMOS transistor Q41 and PMOS transistor Q42are connected between input line 73 and output line 75 with the drainnode of NMOS transistor Q41 coupled to the drain node of PMOS transistorQ42, as shown in FIG. 17. NMOS transistor Q43 and NMOS transistor Q44are connected between input line 73 and output line 77, with the drainnode of transistor Q44 coupled to the source node of transistor Q43.Capacitor CP1 has a first end connected to the junction node betweenNMOS transistor Q41 and PMOS transistor Q42, and a second end connectedto the junction node between NMOS transistor Q43 and NMOS transistorQ44. Capacitor CB0 is connected between ground line 72 and output line75.

[0168] NMOS transistor Q45 and PMOS transistor Q46 are connected betweenground line 72 and input line 74, with the drain node of PMOS transistorQ46 coupled to the drain node of NMOS transistor Q45. NMOS transistorQ47 and NMOS transistor Q48 are connected between output line 76 andoutput line 77 with the drain electrode of transistor Q47 coupled to thesource electrode of transistor Q48. Capacitor CP2 has a first endconnected to the junction node between NMOS transistor Q45 and PMOStransistor Q46, and has a second end connected to the junction nodebetween NMOS transistor Q47 and NMOS transistor Q48. Capacitor CB1 isconnected between ground line 72 and output line 77, and capacitor CB2is connected between output line 76 and output line 77.

[0169] As noted above, MOS transistors Q41 to Q48 are integrated ontothe same p-type semiconductor substrate in the voltage conversioncircuit according to this sixth embodiment, and the configurationthereof is therefore described next below with reference to FIG. 20.

[0170] With reference to FIG. 20A, reference numeral 31 is a p-typesemiconductor substrate, and n-type wells 72/73 are formed in thisp-type semiconductor substrate 31. Two p-type wells 74/75 are formed inn-type well 73.

[0171] NMOS transistor Q45 having a source S, gate G, and drain D isformed in p-type semiconductor substrate 31. PMOS transistor Q46 havinga source S, gate G, and drain D is formed in n-type well 72. NMOStransistors Q47, Q48 each having a source S, gate G, and drain D areformed in p-type wells 74, 75.

[0172] As shown in FIG. 20B, n-type well 73A is formed in p-typesemiconductor substrate 31 and p-type well 74A is formed in n-type well73A. NMOS transistor Q41 having a source S, gate G, and drain D isformed in p-type well 74A.

[0173] MOS transistor Q42 shown in FIG. 17 is configured identically toMOS transistor Q46 shown in FIG. 20, and MOS transistors Q43, Q44 shownin FIG. 17 are configured identically to MOS transistors Q47, Q48 shownin FIG. 20, and these are therefore not shown in FIG. 20.

[0174] NMOS transistors Q47 and Q48 are equivalent to MOS transistorsQ15 and Q16 of FIG. 3, and the conditions for the configuration of wells33 to 35 can therefore be applied to the configuration of wells 73 to75.

[0175] Negative output voltage MV3 is applied to p-type well 74 and thedc input voltage VDD is applied to n-type well 73 so that the pnjunction of p-type well 74 and n-type well 73 is reverse biased as shownin FIG. 20. In addition, negative output voltage VDDy is applied top-type well 75 and dc input voltage VDD is applied to n-type well 73 sothat the pn junction between p-type well 75 and n-type well 73 isreverse biased.

[0176] Furthermore, ground potential VSS is applied to p-typesemiconductor substrate 31 and dc input voltage VDD is applied to n-typewell 73 so that the pn junction between p-type semiconductor substrate31 and n-type well 73 is reverse biased. Note that n-type well 73surrounding NMOS transistors Q47 and Q48 can be set to the groundpotential. Potential VSS is also applied to p-type semiconductorsubstrate 31 and dc input voltage VDD is applied to n-type well 72 sothat the pn junction between p-type semiconductor substrate 31 andn-type well 72 is reverse biased.

[0177] Note that the relationship between dc input voltage VDD,potential VSS, negative output voltage VDDy, and negative output voltageMV3 is VDD>GND>VDDy>MV3.

[0178] Operation of the sixth embodiment thus comprised is describednext with reference to FIG. 17 to FIG. 19.

[0179] Timing signal generator 25E generates timing signals XB2, A2,XB1, A1, B3, and A3 as shown in FIG. 18, and applies these timingsignals to the gate of the corresponding MOS transistors Q41 to Q48 tothereby control switching between the ON and OFF states the MOStransistors Q41 to Q48.

[0180] By using this sort of control, MOS transistors Q41, Q43, Q45 andQ47 turn ON, and MOS transistors Q42, Q44, Q46 and Q48 turn OFF duringan interval T1 shown in FIG. 18. The resulting equivalent circuit duringinterval T1 is as shown in FIG. 19A.

[0181] In contrast, during an interval T2 shown in FIG. 18, the MOStransistors Q42, Q44, Q46 and Q48 turn ON, and the MOS transistors Q41,Q43, Q45 and Q47 turn OFF. The resulting equivalent circuit duringinterval T2 is as shown in FIG. 19B.

[0182] In FIG. 18, it is understood that the states shown in FIGS. 19Aand B alternate repeatedly.

[0183] As shown in FIG. 17, N voltage multiplier circuit 71 receivesinputs Vss and VC, and outputs a positive potential V3 equivalent to Ntimes direct current voltage vC.

[0184] First, in a state that corresponds to the interval T2, in otherwords the state shown in FIG. 19B, capacitor CP1 is coupled across theV3 output from N voltage multiplier 71 and DC voltage VC. Capacitor CP1therefore receives a charge from the N voltage multiplier 71 anddevelops a potential difference across equal to V3-VC. Since V3 is(N·VC), the potential across capacitor CP1 can be written as[(N·VC)−VC], which is Vc·(N−1).

[0185] Subsequently, in a state that corresponds to the interval T1, inother words the state shown in FIG. 19A, the charge in capacitor CP1that was charged during the previous interval T2 is shared withcapacitor CB1. At this stage, the potential difference across capacitorCP1 is equal to |VC·(N−1)|. Therefore, if ground level VSS serves as thereference, then MV3 has a potential as shown below in equation (7).

[0186] Now, from a different perspective, during interval T1, capacitorCP2 is charged by direct current power supply voltage VSS and by thecharge that was stored in capacitor CP1 during the previous interval andwas moved to the capacitor CP2. At this stage, a voltage having anegative output voltage VDDy as shown below in equation (8) isoutputted.

[0187] By repeating the above operation, positive output voltage V3,negative output voltage MV3, and negative output voltage VDDy are outputas shown by equations (6) to (8) below in this sixth embodiment of theinvention.

V3=VC·N  (6)

MV3=(−1)VC·(N−2)  (7)

VDDy=MV3+VDD  (8)

[0188] As described above, the only required external components in thissixth embodiment are the capacitors because the n-fold booster circuit71, timing signal generator 25E, and MOS transistors Q41 to Q48 can beformed in a p-type semiconductor substrate and integrated as an IC chip.As a result, the overall device size can be reduced.

[0189] A voltage conversion circuit according to a seventh embodiment ofthe present invention is described next with reference to FIG. 21 andFIG. 22.

[0190] As shown in FIG. 21 the voltage conversion circuit according tothis seventh embodiment is based on the sixth embodiment of FIG. 17, butadds a logic circuit 77 consisting of an NMOS transistor Q51 and PMOStransistor Q52, and thus forming IC chip 20F.

[0191]FIG. 22 is a section view showing the physical structure of thisvoltage conversion circuit particularly as concerns the MOS transistorsQ51 and Q52 of the output line 77.

[0192] Referring to FIG. 22, reference numeral 31 is a p-typesemiconductor substrate, n-type wells 72 and 81 are formed in p-typesemiconductor substrate 31, p-type well 82 is formed in n-type well 81,and n-type well 83 is formed in p-type well 82. NMOS transistor Q45having a source S, gate G, and drain D is formed in p-type semiconductorsubstrate 31. PMOS transistor Q46 having a source S, gate G, and drain Dis formed in n-type well 72. NMOS transistor Q51 having a source S, gateG, and drain D is formed in p-type well 82. PMOS transistor Q52 having asource S, gate G, and drain D is formed in n-type well 83.

[0193] Other parts of the IC chip 20F according to this seventhembodiment are identical to the IC chip 20E according to the sixthembodiment of FIG. 17, and further description thereof is thus omitted.

[0194] As described above this seventh embodiment is based on the sixthembodiment, and therefore achieves the same operational effects as thesixth embodiment.

[0195] In addition, because an n-type well 83 is further formed insidep-type well 82, and PMOS transistor Q52 is formed inside this n-typewell 83, PMOS transistor Q52 can be used at a lower potential than thepotential (VSS=0 V) of the p-type semiconductor substrate 31, and it istherefore possible to provide a CMOS inverter or other logic circuit 77between two power supplies with a potential lower than the substratepotential.

[0196] A voltage conversion circuit according to an eighth embodiment ofthe present invention is described next with reference to FIG. 23.

[0197] The voltage conversion circuit of this eighth embodiment replacesthe charge-pump type n-fold booster circuit 71 of the sixth embodiment(see FIG. 17) with a synchronous commutating type switching regulator 86as shown in FIG. 23. The switching regulator 86 of FIG. 23 along withthe timing signal generator 25E and MOS transistors Q41 to Q48 of FIG.17 may be formed on the same p-type semiconductor substrate, therebyreducing the number of external components and thus reducing the overallsize.

[0198] As shown in FIG. 23, the switching regulator 86 includesoscillator circuit 87, comparator 88, switching control circuit 89, MOStransistors Q61 and Q62, voltage-dividing resistors RA and RB, coil L1,and capacitor C11. The elements of the part enclosed in the dotted lineare formed on a p-type semiconductor substrate, and coil L1 andcapacitor C11 are externally connected.

[0199] The switching regulator 86 thus comprised controls the switchingof the ON/OFF states of MOS transistors Q61 and Q62 by means ofswitching control circuit 89. First, MOS transistor Q61 is switched ONto store electromagnetic energy in coil L1 by means of the dc supply.Then, MOS transistor Q62 turns ON and the sum of the dc supply voltageand the voltage across coil L1 is taken as output voltage VOUT1.

[0200] Output voltage VOUT1 is voltage divided by the voltage-dividercircuit consisting of resistors RA, RB to produced a stepped-downvoltage representation of VOUT1. Comparator 88 compares the stepped-downvoltage with reference voltage Vrefl. The switching control circuit 89adjusts the ON times of MOS transistors Q61 and Q62 according to theoutput from comparator 88, and thereby holds output voltage VOUT1constant.

[0201] A voltage conversion circuit according to a ninth embodiment ofthe invention is described next with reference to FIG. 24.

[0202] As shown in FIG. 24, the voltage conversion circuit according tothis ninth embodiment outputs positive and negative boosted voltagesfrom a single dc source by using a combination of the synchronouscommutating switching regulator 86 of FIG. 23 to output a positivelyboosted voltage and a synchronous commutating switching regulator 90 tooutput a negatively boosted voltage.

[0203] The switching regulator 86 in FIG. 24 is configured identicallyto the switching regulator 86 shown in FIG. 23, like parts are thereforereferenced by like reference numerals, and further description isomitted. As shown in FIG. 24, switching regulator 90 comprises acomparator 91, switching control circuit 92, MOS transistors Q63 andQ64, voltage-dividing resistors RC and RD, coil L2, and capacitor C12.The functionality of switching regulator 90 is similar to that ofswitching regulator 86 with the exception that the polarity of the powersupplies coupled to switching regulator 90 are reversed so that it mayprovide a negative voltage output.

[0204] The elements of the part enclosed in the dotted line in FIG. 24are formed in a p-type semiconductor substrate in this ninth embodimentusing the same method as in the above first and sixth embodiments, thusforming an IC chip to which coils L1 and L2 and capacitors C11 and C12are externally connected.

[0205] With this ninth embodiment of the invention the NMOS transistorQ64 for generating the negative voltage can be formed in the p-typesemiconductor substrate, the only external components are the coils L1and L2 and capacitors C11 and C12, and the overall device size cantherefore be reduced.

[0206] A voltage conversion circuit according to a tenth embodiment ofthe present invention is described next with reference to FIG. 25 toFIG. 27.

[0207] As shown in FIG. 25, the voltage conversion circuit according tothis tenth embodiment comprises a charge pump type dc-dc converter 95and a plurality of operational amplifiers 96 to 98, forming a dc-dcconverter for converting dc input voltage Vin to a specific dc voltage.

[0208] The dc-dc converter 95 has a charge pump design and outputsvoltages at 0.5, 2, 3, 4, and 5 times the dc input voltage Vin, andthese output voltages are supplied as shown in the figure as the supplyvoltages to the operational amplifiers 96 to 98, which are configured asvoltage followers.

[0209] Output voltage (VIN·5) of dc-dc converter 95 is voltage dividedby voltage-dividing resistors R1 to R3, and these voltage-dividedpotentials are observed at the output terminals of the operationalamplifiers 96 to 98. Note that the internal capacitors of dc-dcconverter 95 and any output stabilizing capacitors are not shown in FIG.25, but are considered to be within the general understanding in theart.

[0210] It should be noted that the dc-dc converter 95 could beconfigured using a plurality of switching regulators, or a combinationof charge pump type dc-dc converters and switching regulators.

[0211]FIG. 26 shows a first exemplary internal configuration foroperational amplifiers 96 to 98. In the present configuration,identified herein as a push mode operational amplifier, the outputcurrent flow is modulated by transistor Q79 functioning as a currentsource.

[0212] As shown in FIG. 26, the push mode operational amplifiers 96-98includes MOS transistors Q71 to Q79, which are formed in a semiconductorsubstrate in the same way as MOS transistors Q11, Q17, Q13, and Q14 ofthe second embodiment (see FIGS. 7 and 9) so that there is no substratebias effect (i.e. no back gate, or back bias, effect) on NMOStransistors Q72 to Q76.

[0213]FIG. 27 shows as second exemplary internal configuration foroperational amplifiers 96 to 98. In the present configuration,identified herein as a pull mode operational amplifier, the outputcurrent is flow modulated by transistor Q89 functioning as a currentdrain.

[0214] As shown in FIG. 27, the pull mode operational amplifiers 96-98includes MOS transistors Q81 to Q89, which are formed in a semiconductorsubstrate in the same way as MOS transistors Q11, Q17, Q13, Q14 in thesecond embodiment so that there is no substrate bias effect (i.e. noback gate, or back bias, effect) on NMOS transistors Q81 and Q87 to Q89.Note that a phase compensation capacitor is omitted in FIG. 26 and FIG.27.

[0215] Various types of amplifiers may be configured as amplifiers96-98. For example, a class B amplifier, also known as a push-pullamplifier, wherein two active devices alternately drive the output nodefor alternate half cycles and neither drive the output for a transitionregion of the operating range between the two cycles, may be use.Alternatively, a class AB amplifier wherein two active devicesalternatively drive the output for alternate half cycles throughout theentire operating range, may also be used.

[0216] As described above, this tenth embodiment of the inventionprovides a circuit configuration whereby the NMOS transistors of theoperational amplifiers 96 to 98 are free of the substrate bias, or backbias, effect, and operation is therefore normal even if an intermediatepotential output from dc-dc converter 95 is applied as the sourcevoltage of the operational amplifiers 96 to 98.

[0217] It will also be noted that by applying an intermediate potentialfrom the dc-dc converter 95 as the supply voltage VDD, VSS to theoperational amplifiers 96 to 98, power consumption by the operationalamplifiers can be suppressed and power conversion efficiency issignificantly improved when a negative overcurrent is supplied. Forexample, when negative overcurrent Io flows from operational amplifier97 in the direction shown in FIG. 25, a current of five times Io wouldflow to the input side of a conventional circuit, but is reduced to onlythree times Io with the design shown in FIG. 25.

[0218] A voltage conversion circuit according to an eleventh embodimentof the present invention is described next with reference to FIG. 28.

[0219] The voltage conversion circuit according to this eleventhembodiment uses a process whereby the circuit of the seventh embodimentas shown in FIG. 21 is integrated as shown in FIG. 22, for example, andassembles p-channel and channel MOS transistors to a desired potentialirrespective of the system supply voltage.

[0220] This eleventh embodiment is therefore a dc-dc converter combininga voltage converter 101 comprising a charge-pump type dc-dc converterand switching regulator arrangement with plural operational amplifiers102 to 104 so as to generate a specific positive and negative voltagebased on the dc input voltage Vin.

[0221] The voltage converter 101 outputs, for example, a positivevoltage that is three or five times the dc input voltage Vin, andnegative voltages at −1 and −3 or −5 times the dc input voltage Vin.These output voltages are supplied as the source voltages to theoperational amplifiers 102 to 104 configured as voltage followers asshown in FIG. 28. Output voltages from the voltage converter 101 arealso voltage divided by voltage dividing resistors R11 to R13, and thevoltage-divided voltages are taken from the output terminals of theoperational amplifiers 102 to 104.

[0222] Advantages of the Invention

[0223] As will be known from the preceding description, the MOStransistors used for voltage conversion can be formed in the same p-typesemiconductor substrate with the present invention, thereby reducing theexternally disposed parts to the capacitors only and making it possibleto reduce the overall size while maintaining high power conversionefficiency.

[0224] It is also possible according to the present invention to formthe MOS transistors used for voltage conversion in the same n-typesemiconductor substrate, thereby reducing the externally disposed partsto the capacitors only and making it possible to reduce the overall sizewhile maintaining high power conversion efficiency.

[0225] While the invention has been described in conjunction withseveral specific embodiments, it is evident to those skilled in the artthat many further alternatives, modifications and variations will beapparent in light of the foregoing description. Thus, the inventiondescribed herein is intended to embrace all such alternatives,modifications, applications and variations as may fall within the spiritand scope of the appended claims.

What is claimed is:
 1. A voltage conversion circuit comprising: an inputnode for receiving an input DC voltage; a first output node and a secondoutput node; a plurality of MOS transistors; a plurality of capacitivedevices for storing and transferring charge; said plurality of MOStransistors forming a switching network for routing charge among saidplurality of capacitive devices to produce a predetermined positivevoltage at said first output node and a predetermined negative voltageat said second output node, said switching network including PMOS andNMOS transistors for producing said predetermined positive voltage atsaid first output node, and including at least one NMOS transistor forproducing said negative voltage at said second output node; wherein theNMOS transistors for producing said positive voltage are formed in ap-type semiconductor substrate; the PMOS transistors for producing saidpositive voltage are formed in a first well of n-type conductivityformed in said p-type semiconductor substrate; and said p-typesemiconductor has a second well of n-type conductivity, and the NMOStransistor for producing said negative voltage is formed in a third wellof p-type conductivity formed in said second well.
 2. The voltageconversion circuit of claim 1, further comprising an ON/OFF controlmeans for switching the ON/OFF state of said plurality of MOStransistors, said ON/OFF control means being formed on said p-typesemiconductor substrate.
 3. The voltage conversion circuit of claim 1,wherein at least one of said plurality of MOS transistors has an offsetarea in said p-type semiconductor substrate around its gate insulationlayer, said offset area being a low concentration impurity layerdisposed below a LOCOS layer in said semiconductor substrate.
 4. Thevoltage conversion circuit of claim 1, wherein said second well ofn-type conductivity and said p-type semiconductor substrate aremaintained at substantially the same voltage potential during operation.5 The voltage conversion circuit of claim 4, wherein said second well ofn-type conductivity and said third well of p-type conductivity aremaintained in a reversed bias condition during operation.
 6. The voltageconversion circuit of claim 1, wherein said second well of n-typeconductivity and said p-type semiconductor substrate are maintained in areversed bias condition during operation
 7. The voltage conversioncircuit of claim 6, wherein said second well of n-type conductivity andsaid third well of p-type conductivity are maintained in a reversed biascondition during operation.
 8. The voltage conversion circuit of claim1, further having a bias voltage receiving node coupled to said secondwell of n-type conductivity for maintaining said second well at avoltage potential higher than said third well of p-type conductivity andsaid p-type substrate.
 9. A voltage conversion circuit comprising: aninput node for receiving an input DC voltage; a first output node and asecond output node; a plurality of MOS transistors; a plurality ofcapacitive devices for storing and transferring charge; said pluralityof MOS transistors forming a switching network for routing charge amongsaid plurality of capacitive devices to produce a predetermined positivevoltage at said first output node and a predetermined negative voltageat said second output node, said switching network including PMOS andNMOS transistors for producing said predetermined positive voltage atsaid first output node, and including at least one NMOS transistor forproducing said negative voltage at said second output node; wherein: atleast one of the NMOS transistors used for producing said positivevoltage is formed in a p-type semiconductor substrate; the PMOStransistors used for producing said positive voltage are formed in afirst well of n-type conductivity formed in said p-type semiconductorsubstrate; said p-type substrate has a second well of n-typeconductivity; and at least one other of the NMOS transistors used forproducing said positive voltage and the NMOS transistor used forproducing said negative voltage are formed in a third well of p-typeconductivity formed in said second well.
 10. The voltage conversioncircuit of claim 9, further comprising an ON/OFF control means forswitching the ON/OFF state of said plurality of MOS transistors, saidON/OFF control means being formed on said p-type semiconductorsubstrate.
 11. The voltage conversion circuit of claim 9, wherein atleast one of said plurality of MOS transistors has an offset area insaid p-type semiconductor substrate around its gate insulation layer,said offset area being a low concentration impurity layer disposed belowa LOCOS layer in said semiconductor substrate.
 12. The voltageconversion circuit of claim 9, wherein said second well of n-typeconductivity and said p-type semiconductor substrate are maintained atsubstantially the same voltage potential during operation.
 13. Thevoltage conversion circuit of claim 12, wherein said second well ofn-type conductivity and said third well of p-type conductivity aremaintained in a reversed bias condition during operation.
 14. Thevoltage conversion circuit of claim 9, wherein said second well ofn-type conductivity and said p-type semiconductor substrate aremaintained in a reversed bias condition during operation
 15. The voltageconversion circuit of claim 14, wherein said second well of n-typeconductivity and said third well of p-type conductivity are maintainedin a reversed bias condition during operation.
 16. The voltageconversion circuit of claim 9, further having a bias voltage receivingnode coupled to said second well of n-type conductivity for maintainingsaid second well at a voltage potential higher than said third well ofp-type conductivity and said p-type substrate.
 17. A voltage conversioncircuit comprising: an input node for receiving an input DC voltage; afirst output node and a second output node; a plurality of MOStransistors; a plurality of capacitive devices for storing andtransferring charge; said plurality of MOS transistors forming aswitching network for routing charge among said plurality of capacitivedevices to produce a predetermined positive voltage at said first outputnode and a predetermined negative voltage at said second output node,said switching network including PMOS and NMOS transistors for producingsaid predetermined positive voltage at said first output node, andincluding PMOS and NMOS transistors for producing said negative voltageat said second output node; wherein: the NMOS transistors used forproducing said negative voltage are formed in a p-type semiconductorsubstrate; the PMOS transistors used for producing said positive voltageand the PMOS transistors used for producing said negative voltage areformed in a first well of n-type conductivity formed in said p-typesemiconductor substrate; said p-type substrate has a second well ofn-type conductivity; and the NMOS transistors used for producing saidpositive voltage are formed in a third well of p-type conductivity,which is formed in said second well.
 18. The voltage conversion circuitof claim 17, further comprising an ON/OFF control means for switchingthe ON/OFF state of said plurality of MOS transistors, said ON/OFFcontrol means being formed on said p-type semiconductor substrate. 19.The voltage conversion circuit of claim 17, wherein at least one of saidplurality of MOS transistors has an offset area in said p-typesemiconductor substrate around its gate insulation layer, said offsetarea being a low concentration impurity layer disposed below a LOCOSlayer in said semiconductor substrate.
 20. The voltage conversioncircuit of claim 17, wherein said second well of n-type conductivity andsaid p-type semiconductor substrate are maintained at substantially thesame voltage potential during operation.
 21. The voltage conversioncircuit of claim 20, wherein said second well of n-type conductivity andsaid third well of p-type conductivity are maintained in a reversed biascondition during operation.
 22. The voltage conversion circuit of claim17, wherein said second well of n-type conductivity and said p-typesemiconductor substrate are maintained in a reversed bias conditionduring operation
 23. The voltage conversion circuit of claim 22, whereinsaid second well of n-type conductivity and said third well of p-typeconductivity are maintained in a reversed bias condition duringoperation.
 24. The voltage conversion circuit of claim 17, furtherhaving a bias voltage receiving node coupled to said second well ofn-type conductivity for maintaining said second well at a voltagepotential higher than said third well of p-type conductivity and saidp-type substrate.
 25. A voltage conversion circuit comprising: an inputnode for receiving an input DC voltage; a first output node and a secondoutput node; a plurality of MOS transistors; a plurality of capacitivedevices for storing and transferring charge; said plurality of MOStransistors forming a switching network for routing charge among saidplurality of capacitive devices to produce a predetermined positivevoltage at said first output node and a predetermined negative voltageat said second output node, said switching network including at leastone PMOS transistor for producing said positive voltage at said firstoutput node, and including PMOS and NMOS transistors for producing saidpredetermined negative voltage at said second output node; wherein: thePMOS transistors used for producing said negative voltage are formed inan n-type semiconductor substrate; the NMOS transistors used forproducing said negative voltage are formed in a first well of p-typeconductivity in said n-type semiconductor substrate; said n-typesubstrate has a second well of p-type conductivity; and the PMOStransistor used for producing said positive voltage is formed in a thirdwell of n-type conductivity, which is formed in said second well.
 26. Avoltage conversion circuit as described in claim 25, further comprisingan ON/OFF control means for switching the ON/OFF state of said pluralityof MOS transistors, said ON/OFF control means being formed on saidn-type semiconductor substrate.
 27. A voltage conversion circuit asdescribed in claim 25, wherein at least one of said plurality of MOStransistors has an offset area in said n-type semiconductor substratearound its gate insulation layer, said offset area being a lowconcentration impurity layer disposed below a LOCOS layer in saidsemiconductor substrate.
 28. The voltage conversion circuit of claim 25,wherein said second well of n-type conductivity and said p-typesemiconductor substrate are maintained at substantially the same voltagepotential during operation.
 29. The voltage conversion circuit of claim28, wherein said second well of n-type conductivity and said third wellof p-type conductivity are maintained in a reversed bias conditionduring operation.
 30. The voltage conversion circuit of claim 25,wherein said second well of n-type conductivity and said p-typesemiconductor substrate are maintained in a reversed bias conditionduring operation
 31. The voltage conversion circuit of claim 30, whereinsaid second well of n-type conductivity and said third well of p-typeconductivity are maintained in a reversed bias condition duringoperation.
 32. The voltage conversion circuit of claim 25, furtherhaving a bias voltage receiving node coupled to said second well ofn-type conductivity for maintaining said second well at a voltagepotential higher than said third well of p-type conductivity and saidp-type substrate.
 33. A voltage conversion circuit comprising: an inputnode for receiving an input DC voltage; a first output node and a secondoutput node; a booster circuit for boosting said input DC voltage by afactor of n and outputting the boosted voltage as a positive voltage atsaid first output node; a capacitive device; a plurality of MOStransistors forming a switching network for transferring charge fromsaid booster circuit to said capacitive device, the resultant voltageacross said capacitive device being output as a negative voltage at saidsecond output node, said switching network including PMOS and NMOStransistors used in the generation of the negative voltage across saidcapacitive device; wherein a first group of said NMOS transistors areformed in a p-type semiconductor substrate; said PMOS transistors areformed in a first well of n-type conductivity formed in said p-typesemiconductor substrate; said p-type substrate includes a second well ofn-type conductivity; and a second group of said NMOS transistors areformed in a third well of p-type conductivity, which is formed in saidsecond well.
 34. A voltage conversion circuit as described in claim 33,further comprising an ON/OFF control means for switching the ON/OFFstate of said plurality of MOS transistors , said ON/OFF control meansand said booster circuit being formed on said p-type semiconductorsubstrate.
 35. A voltage conversion circuit as described in claim 33,wherein at least one of said plurality of MOS transistors has an offsetarea in said semiconductor substrate around its gate insulation layer,said offset area being a low concentration impurity layer disposed belowa LOCOS layer in the semiconductor substrate.
 36. A voltage conversioncircuit as described in claim 33, wherein a fourth well of n-typeconductivity is further formed in said third well, and a PMOS transistornot part of said switching network and used in a logic circuit is formedin said fourth well.
 37. A voltage conversion circuit as described inclaim 33, wherein a fourth well of n-type conductivity is further formedin said third well, and a PMOS transistor used for generating saidnegative voltage is formed inside said fourth well.
 38. The voltageconversion circuit of claim 33, wherein said second well of n-typeconductivity and said p-type semiconductor substrate are maintained atsubstantially the same voltage potential during operation.
 39. Thevoltage conversion circuit of claim 38, wherein said second well ofn-type conductivity and said third well of p-type conductivity aremaintained in a reversed bias condition during operation.
 40. Thevoltage conversion circuit of claim 33, wherein said second well ofn-type conductivity and said p-type semiconductor substrate aremaintained in a reversed bias condition during operation
 41. The voltageconversion circuit of claim 40, wherein said second well of n-typeconductivity and said third well of p-type conductivity are maintainedin a reversed bias condition during operation.
 42. The voltageconversion circuit of claim 33, further having a bias voltage receivingnode coupled to said second well of n-type conductivity for maintainingsaid second well at a voltage potential higher than said third well ofp-type conductivity and said p-type substrate.